A typical variable resistance memory device, or memristor, may be “programmed” to have two logic states, such as a low resistance state (on-state) and a high resistance state (off-state). In order to program the memristor into a low resistance state, a potential difference may be applied across a memory stack of the memristor. The potential difference may form one or more conductive pathways through the memory device, thereby decreasing the resistance of the memristor. In order to program the memristor into a high resistance state, a reverse potential difference may be applied across the memory stack. The reverse potential difference may alter, eliminate, or reduce the one or more conductive pathways, increasing the resistance of the memristor. The programmed resistance may be permanent, or semi-permanent, until changed by another applied potential. To read the resistance state of the memristor, a smaller potential difference (e.g., a voltage that is insufficient to change the resistance state) may be applied to the memory stack and a resultant current may be measured to determine the resistance state.
U.S. Pat. No. 7,087,919, filed on Apr. 7, 2004 and entitled, “Layered Resistance Variable Memory Device and Method of Fabrication,” describes an example of a variable resistance memory device that relies on ion conduction to alter a resistance of the device. The device has at least one layer of silver-selenide between a first chalcogenide glass layer and a conductive adhesion layer, which may also be a chalcogenide glass layer. When a potential difference is placed across the device, the silver may form one or more conductive channels through the chalcogenide glass layer, thereby altering a resistance of the device. U.S. Pat. No. 7,087,919 is hereby incorporated by reference in its entirety.
U.S. Pat. No. 7,190,048, filed on Jul. 19, 2004 and entitled “Resistance Variable Memory Device and Method of Fabrication,” describes another example of a variable resistance memory device that includes a stack with at least one layer of tin-chalcogenide proximate a first chalcogenide glass layer. During a conditioning step, tin-selenide from the tin-chalcogenide layer is incorporated into the chalcogenide glass layer to form conducting channels. Movement of silver ions into or out of that conducting channel during subsequent programming forms a conductive pathway, which causes a detectable resistance change across the memory device. U.S. Pat. No. 7,190,048 is hereby incorporated by reference in its entirety.
One potential challenge associated with typical memristor devices is that when the memristor is in a low resistance state, a high current may be drawn through the memristor in response to an applied voltage potential. The high current may result in high power consumption, which may decrease the economic value, or feasibility, of using typical memristor devices for some applications such as high density arrays. The high current may also produce heat that may alter the chemical structure of the device stack. Another potential problem associated with typical memristors is that the dynamic range of programmable resistance may be limited. For example, the dynamic range of programmable resistance of a typical memristor may only enable binary resistance states (e.g., an on-state or an off-state). As such, typical memristors may not be suitable for applications that depend on multiple discrete states or a continuous range of states.